1. Field of the Invention
This invention relates to analog and digital processors and methods, and more particularly to analog and digital circuits, systems, and methods for charge coupled devices (CCDs), CMOS imagers, and cameras.
2. Description of the Related Art
Charge coupled device (CCD) camera systems are configured to capture signals according to many different CCD output formats and pixel configurations. One such CCD camera includes a sensor array, a high voltage CCD driver for driving the sensor array, and a DCxe2x80x94DC converter. The sensor array drives an analog processor which is in turn connected to a digital processor. The analog processor converts the signals received from the sensor array from an analog form into digital data. Such a camera produces a digital still image with up to 8kx8k pixels. The sensor array includes a grid of sensing elements arranged in a plurality of lines distributed across a vertical axis. Each line has a predetermined horizontal width. The CCD sensor array requires vertical and horizontal timing signals. Current CCD systems fail to have analog processors which are able directly to provide both analog and vertical timing systems to the CCD array. This makes it technically difficult to control the timing of a CCD array.
Further, many CCD arrays require the provision of several control currents to enable operation of the CCD array. Provision of there control currents is difficult to implement technically with the digital processing circuitry used to operate and control the associated CCD arrays. Accordingly, it is desirable to enable the convenient and controllable provision of desired control currents to a CCD array.
Many analog processors used with CCD systems use analog-to-digital converters having a limited dynamic range. Therefore, there is a need for a processor to have an extended dynamic range to be able to process the CCD output into digital formatted data to enable user controlled hardware or software data processing leading to production of viewable digital images.
There is a further need to control output resolution of the analog and digital subsystems in terms of bit-width. According to one known CCD format, in order to obtain a still image with acceptable resolution and contrast from a CCD, a minimum of 10 bits of resolution is desired. To practically capture a CCD image, the data read-out time from the CCD is very limited. Accordingly, one such front end interface which accepts CCD data for conversion into digital form operates typically up to 16 MHz with a 10-bit analog-to-digital converter. Such a camera can produce a digital still image with up to 8kx8k pixels.
The feature set available in known CCD camera systems is increasing to include enhanced functionality, as well as extended dynamic range. Such extended functionality comes at a price in terms of electronic complexity and power consumption. For example, some current camera systems include a liquid crystal display (LCD) screen to enable viewing of images in a real-time viewfinder. This requires the CCD and associated processing chips to run in a video mode and to remain powered up while the screen is in use. This can dissipate a large amount of power that tends to shorten battery life. In such an operational mode, front end circuitry is operated at a resolution level which is unnecessary for driving the relatively low resolution LCD display, thereby consuming power needlessly. Accordingly, there is a need to enable low power operation of the analog and digital subsystems in CCD camera and imager systems that convert analog data into digital signal forms for user applications. There is a further need for low power operation of analog and digital subsystems generally that convert analog data into digital signal forms.
According to the present invention, a processing system for a charge coupled device (CCD) or CMOS imaging system includes a multi-mode, multiple current level, correlated double sampler and variable gain (CDS/VGA) circuit for receiving data from a CCD system. The architecture of the processing system also includes a black level clamp and an A/D conversion module having a selectable bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip analog front end produces digitized CCD data in a bit format corresponding to selected current level and data resolution. The VGA amplifier includes circuitry to enable selected data resolution levels respectively for still image capture and separate video display on another viewing screen. The processing-system according to the present invention further includes timing circuitry adapted to control both vertical and horizontal timing of the sensor array elements in the CCD. The CCD requires bias voltages of various magnitudes, which are provided according to the present invention, including for example, a substrate bias voltage. According to the present invention, up to two CCD bias voltages are generated from currents supplied with an analog processor including first and second digital-to-analog converters. According to one embodiment of the present invention, the first and second digital-to-analog converters are controlled with signals provided by the user through serial interface circuitry.
According to a further embodiment of the present invention, a processing system for an imager device includes a sensor for producing an image signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS and VGA circuits for producing output signals of expanded dynamic range including but not limited to a thirteen bit wide digital output, a gain adjust block (GAB) coupled to said ADC, a black level adjustment circuit including a clamp setting, a compander circuit coupled to said GAB for reducing the output bitwidth, a multiplexer permitting selection of output signals of selected bit-width, and a phase-lock-loop (PLL) for controlling a multi-sync timing generator including an analog clock generator (ACG). The processing system according to the present invention further includes timing circuitry adapted to control both vertical and horizontal timing of the sensor array elements in the CCD.
According to another embodiment of the present invention, a signal processing system (SPS) on an integrated substrate for a video camera includes analog front-end (AFE) circuitry with digital outputs selectable for multiple bitwidths and having selectable high and low resolution (preview) output modes, and digital signal processing system (DSPS) circuitry connected to the analog front-end (AFE) circuitry. According to the present invention, a signal processing system (SPS) for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to the VGA circuit, a digital gain circuit (DGC) coupled to the ADC, and a compander circuit coupled to said DGC for reducing the output bitwidth. According to the present invention, gain control of a signal processing system for an imager device includes a correlated double sampler, and variable gain amplifier circuit (CDSVGA) for receiving data from the imaging system, and a gain adjust block (GAB) coupled to said ADC for controlling the level of gain provided signals from the camera system according to the present invention. According to the present invention, signal processing circuitry for a video camera has first and second data processing subsystems including an analog front-end (AFE) and a digital signal processing system (DSPS) connected to the analog front-end (AFE). The AFE according to the present invention further includes timing circuitry adapted to control both vertical and horizontal timing of the sensor array elements in the CCD array.
The signal processing system according to the present invention performs signal processing functions for a CCD or CMOS imaging camera. A complete digital camera according to one embodiment of the present invention includes in part a sensor array, a vertical driver, a DC-DC converter, the AFE and the DSPS. The AFE data processing subsystem according to the present invention receives a CCD output from the CCD camera, performs analog signal processing, and produces a digital output which can be converted to a form suitable for image display. The processing system according to the present invention further includes timing circuitry adapted to control both vertical and horizontal timing of the sensor array elements in the CCD array. The DSPS data processing subsystem according to the present invention accepts the digital output of the AFE data processing subsystem, performs digital processing on the received digital output of the AFE, and according to one embodiment of the present invention outputs a data product suitable for presentation on a user selected display, without directly influencing CCD horizontal or vertical timing.
According to one embodiment of the present invention, a processing system for an imager device includes a camera system for producing a desired imager signal which operates in a reduced power or preview mode. Such a system according to the present invention includes a correlated double sample (CDS) circuit for receiving data from a selected imager, a multi-mode (selectably high or low current) variable gain amplifier (VGA), a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said CDS circuit. The low power mode enables production of an ADC output signal of selectable higher or lower resolution. The processing system according to the present invention includes a gain adjust block (GAB) coupled to the ADC, a black level adjustment circuit including a predetermined clamp setting, a compander circuit coupled to said GAB for further reducing the output bit-width, a multiplexer permitting selection of output signals of selected bit-width, and a phase-lock-loop (PLL) for controlling a multi-sync timing generator including an analog clock generator (ACG). According to the present invention, the compander provides a bit-width reduction which compresses the output so that a smaller bit-width signal can retain the same dynamic range as a larger bit-width signal. The ADC output bit-width sacrifices only an acceptable level of resolution, in accordance with the present invention. According to one embodiment of the present invention, by reducing the resolution requirement of the camera system front end to a selected number of bits during a still camera viewfinder video mode of operation, the power dissipated by the camera system is reduced substantially. In particular according to one embodiment of the present invention, a signal processing system (SPS) on an integrated substrate for a camera has a reduced power preview mode. The camera includes analog front-end (AFE) circuitry with digital outputs selectable for multiple bitwidths and having selectable high and low resolution (preview) output modes, and digital signal processing system (DSPS) circuitry connected to the analog front-end (AFE) circuitry.